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ds096 (v3.2) march 8, 2007 www.xilinx.com 1 product specification ? 2002-2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 7.1 ns pin-to-pin delays - as low as 14 a quiescent current ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in multiple package options - 208-pin pqfp with 173 user i/o - 256-ball ft (1.0mm) bga with 212 user i/o - 324-ball fg (1.0mm) bga with 270 user i/o - pb-free available for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - unsurpassed low power management datagate enable signal control - four separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers clock divider (divide by 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - advanced design security - pla architecture superior pinout retention 100% product term routability across function block - open-drain output option for wired-or and led drive - optional bus-hold, 3-state or weak pullup on selected i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels sstl2-1, sstl3-1, and hstl-1 i/o compatibility - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 512-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of thirty two function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt-trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. circuitry has also been included to divide one externally supplied global clock (gck2) by eight different selections. this yields divide by even and odd clock frequencies. the use of the clock divide (division by 2) and dualedge flip-flop gives the resultant coolclock feature. datagate is a method to selectively disable inputs of the cpld that are not of interest during certain points in time. 0 xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 00 product specification r
xc2c512 coolrunner-ii cpld 2 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r by mapping a signal to the datagate function, lower power can be achieved due to reduction in signal switching. another feature that eases voltage translation is i/o bank- ing. four i/o banks are available on the coolrunner-ii 512 macrocell device that permits easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. the coolrunner-ii 512 macrocell cpld is i/o compatible with various jedec i/o standards (see table 1 ). this device is also 1.5v i/o compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ realdigital, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high-performance and low power operation. supported i/o standards the coolrunner-ii 512 macrocell features lvcmos, lvttl, sstl, and hstl i/o implementations. see ta b le 1 for i/o standard voltages. the lvttl i/o standard is a gen- eral purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. both hstl and sstl i/o standards make use of a v ref pin for jedec compliance. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. table 1: i/o standards for xc2c512 (1) iostandard attribute output v ccio input v ccio input v ref board termination voltage v tt lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 (2) 1.5 1.5 n/a n/a hstl_1 1.5 1.5 0.75 0.75 sstl2_1 2.5 2.5 1.25 1.25 sstl3_1 3.3 3.3 1.5 1.5 (1) for information on vref pins, see xapp399 . (2) lvcmos15 requires schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 20 40 60 80 100 120 140 160 180 typical i cc (ma) 0.025 17.22 34.37 52.04 69.44 86.85 105.13 122.68 140.23 157.78 notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). frequency (mhz) ds096_01_030705 i cc (ma) 0 0 50 100 150 200 180 160 120 80 20 140 60 100 40 250
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits -0.5 to 4.0 v v ccaux jtag input supply voltage -0.5 to 4.0 v v in (1) input voltage relative to ground (1) ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output (1) ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux jtag programming 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current commercial v cc = 1.9v, v ccio = 3.6v 50 240 a i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 150 400 a i cc (1) dynamic current f = 1 mhz - 1 ma f = 50 mhz - 55 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?1 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block) tested at v cc = v ccio = 1.9v. 2. see quality and reliability section of the coolrunner-ii family data sheet.
xc2c512 coolrunner-ii cpld 4 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r lvcmos 3.3v and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.8v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.5v dc voltage specifications (1) symbol parameter test conditions min. max. units v ccio input source voltage - 3.0 3.6 v v ih high level input voltage - 2 3.9 v v il low level input voltage - ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 2.3 2.7 v v ih high level input voltage - 1.7 v ccio + 0.3 (1)) v v il low level input voltage - ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1ma, v ccio = 2.3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 1.7 1.9 v v ih high level input voltage - 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage - ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 1.6 v v ih high level input voltage - 0.5 x v ccio 0.8 x v ccio v v il low level input voltage - 0.2 x v ccio 0.5 x v ccio v
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 5 product specification r schmitt trigger input dc voltage specifications sstl2-1 dc voltage specifications sstl3-1 dc voltage specifications v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage 1.4 3.9 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v symbol parameter test conditions min. typ max. units v ccio input source voltage 2.3 2.5 2.7 v v ref (1) input reference voltage 1.15 1.25 1.35 v v tt (2) termination voltage v ref ? 0.04 1.25 v ref + 0.04 v v ih high level input voltage v ref + 0.18 - 3.9 v v il low level input voltage ?0.3 - v ref ? 0.18 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.62 - - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - - 0.54 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref 2. v tt of transmitting device must track v ref of receiving devices symbol parameter test conditions min. typ max. units v ccio input source voltage 3.0 3.3 3.6 v v ref (1) input reference voltage 1.3 1.5 1.7 v v tt (2) termination voltage v ref ? 0.05 1.5 v ref + 0.05 v v ih high level input voltage v ref + 0.2 - v ccio + 0.3 v v il low level input voltage ?0.3 - v ref ? 0.2 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 1.1 - - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - - 0.7 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref 2. v tt of transmitting device must track v ref of receiving devices symbol parameter test conditions min. max. units
xc2c512 coolrunner-ii cpld 6 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r hstl1 dc voltage specifications symbol parameter test conditions min. typ max. units v ccio input source voltage 1.4 1.5 1.6 v v ref (1) input reference voltage 0.68 0.75 0.90 v v tt (2) termination voltage - v ccio x 0.5 - v v ih high level input voltage v ref + 0.1 - 1.9 v v il low level input voltage ?0.3 - v ref ? 0.1 v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.4 - - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - - 0.4 v notes: 1. v ref should track the variations in v ccio , also peak-to-peak ac noise on v ref may not exceed 2% v ref 2. v tt of transmitting device must track v ref of receiving devices
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 7 product specification r ac electrical characteristics over recommended operating conditions symbol parameter -7 -10 units min. max. min. max. t pd1 propagation delay (single p-term) - 7.1 - 9.2 ns t pd2 propagation delay (or array) - 7.5 - 10.0 ns t sud direct input register set-up time 3.4 - 4.0 - ns t su1 setup time fast (single p-term) 2.6 - 3.1 - ns t su2 setup time (or array) 3.0 - 3.9 - ns t h direct input register hold time 0 - 0 - ns t h p-term hold time 0 - 0 - ns t co clock to output - 5.8 - 7.9 ns f toggle (1) internal toggle rate - 250 - 166 mhz f system1 (2) maximum system frequency - 179 - 128 mhz f system2 (2) maximum system frequency - 167 - 116 mhz f ext1 (3) maximum external frequency - 119 - 91 mhz f ext2 (3) maximum external frequency - 114 - 85 mhz t psud direct input register p-term clock setup time 2.1 - 2.8 - ns t psu1 p-term clock setup time (single p-term) 1.1 - 1.7 - ns t psu2 p-term clock setup time (or array) 1.5 - 2.5 - ns t phd direct input register p-term clock hold time 0.1 - 0.4 - ns t ph p-term clock hold 1.3 - 1.7 - ns t pco p-term clock to output - 7.3 - 9.3 ns t oe /t od global oe to output enable/disable - 6.5 - 9.2 ns t poe /t pod p-term oe to output enable/disable - 7.5 - 10.2 ns t moe /t mod macrocell driven oe to output enable/disable - 8.6 - 12.5 ns t pao p-term set/reset to output valid - 7.6 - 11.6 ns t ao global set/reset to output valid - 7.5 - 11.5 ns t suec register clock enable setup time 2.8 - 3.2 - ns t hec register clock enable hold time 0 - 0 - ns t cw global clock pulse width high or low 2.0 - 3.0 - ns t pcw p-term pulse width high or low 7.5 - 10.0 - ns t aprpw asynchronous preset/reset pulse width (high or low) 7.5 - 10.0 - ns t dgsu set-up before datagate latch assertion 0.0 - 0.0 - ns t dgh hold to datagate latch assertion 4.0 - 6.0 - ns t dgr datagate recovery to new data - 9.3 - 11.0 ns t dgw datagate low pulse width 3.0 - 5.0 - ns t cdrsu cdrst setup time before falling edge gclk2 1.7 - 2.5 - ns t cdrh hold time cdrst after falling edge gclk2 0 - 0 - ns t config (4) configuration time - 400 - 400 s notes: 1. f toggle is the maximum clock frequency to which a t-flip flop can reliably toggle (see the coolrunner-ii family data sheet for more information). 2. f system1 (1/t cycle ) is the internal operating frequency for a device fully populated with 16-bit resetable binary counter through one p-term per macrocell while f system2 is through the or array. 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array 4. typical configuration current during t config is approximately 15ma
xc2c512 coolrunner-ii cpld 8 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r internal timing parameters (1) symbol parameter (1) -7 -10 units min. max. min. max. buffer delays t in input buffer delay - 3.1 - 3.8 ns t din direct data register input delay - 4.4 - 5.5 ns t gck global clock buffer delay - 2.4 - 3.3 ns t gsr global set/reset buffer delay - 3.8 - 4.6 ns t gts global 3-state buffer delay - 2.9 - 3.7 ns t out output buffer delay - 3.0 - 3.9 ns t en output buffer enable/disable delay - 3.6 - 5.5 ns p-term delays t ct control term delay - 0.8 - 0.9 ns t logi1 single p-term delay adder - 0.5 - 0.8 ns t logi2 multiple p-term delay adder - 0.4 - 0.8 ns macrocell delay t pdi input to output valid - 0.5 - 0.7 ns t sui setup before clock 1.4 - 1.8 - ns t hi hold after clock 0 - 0 - ns t ecsu enable clock setup time 1.3 - 1.8 - ns t echo enable clock hold time 0 - 0 - ns t coi clock to output valid - 0.4 - 0.7 ns t aoi set/reset to output valid - 0.7 - 3.0 ns t cdbl clock doubler delay - 0 - 0 ns feedback delays t f feedback delay - 3.3 - 4.5 ns t oem macrocell to global oe delay - 2.2 - 3.0 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 3.0 - 4.0 ns t out15 output adder - 0.8 - 1.0 ns t slew15 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 2.0 - 3.0 ns t out18 output adder - 0 - 0 ns t slew18 output slew rate adder - 2.5 - 4.0 ns
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 9 product specification r switching characteristics ac test circuit i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.6 - 1.0 ns t hys25 hysteresis input adder - 1.5 - 3.0 ns t out25 output adder - 0.8 - 2.0 ns t slew25 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.5 - 2.0 ns t hys33 hysteresis input adder - 1.2 - 3.0 ns t out33 output adder - 1.2 - 3.0 ns t slew33 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays hstl, sstl sstl2-1 input adder to t in , t din , t gck , t gsr ,t gts - 0.4 - 1.0 ns output adder to t out --0.5-0.0ns sstl3-1 input adder to t in , t din , t gck , t gsr ,t gts - 0.6 - 1.0 ns output adder to t out - 0.0 - 0.0 ns hstl-1 input adder to t in , t din , t gck , t gsr ,t gts - 0.8 - 1.0 ns output adder to t out - 0.0 - 0.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (1) (continued) symbol parameter (1) -7 -10 units min. max. min. max. figure 2: derating curve for t pd number of outputs switching 1 2 4 8 16 6.0 6.4 6.8 v cc = v ccio = 1.8v @ 25 o c t pd2 (ns) 7.0 6.6 6.2 ds096_02_022003 figure 3: load circuit r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 lvcmos25 lvcmos18 lvcmos15 c l includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs. r 1 268 275 188 112.5 150 r 2 235 275 188 112.5 150 c l 35 pf 35 pf 35pf 35pf 35pf ds_act_08_14_0 2 test point
xc2c512 coolrunner-ii cpld 10 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r typical i/o output curves the i/v curve illustrates the nominal amount of current that an i/o can source/sink at different voltage levels. figure 4: typical i/v curves for xc2c512 vo (output volts) xc512voio_all02200 3 io (output current ma) 0 0 80 20 40 60 3.0 2.5 2.0 1.5 1.0 .5 3 .5 3.3v 1.5v 1.8v 2.5v i ol
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 11 product specification r 11 pin descriptions function block macro- cell pq208 ft256 fg324 i/o bank 1(gts0) 1 7 d4 c1 2 126b2c22 1(gts3) 3 5 e3 b1 2 144c3b22 15---- 16---- 17---- 18---- 19---- 110---- 111---- 112---- 1(gts2) 13 3 d3 d3 2 1142b3c32 1 15 208 b4 a1 2 1(gsr) 16 206 c4 a2 2 21-a1d22 228-d12 23-d2f42 24--f32 25---- 26---- 27---- 28---- 29---- 210---- 211---- 212---- 213-c2e22 2(gts1) 14 9 e5 e1 2 2 15 10b1f2 2 21612e4g42 31205-b32 32-a2c42 33203-b42 34-c5c52 35202a3b52 36---- 37---- 38---- 39---- 310---- 311---- 312---- 3 13 201 e7 a3 2 3 14 - a4 a4 2 3 15 200 c6 d6 2 3 16 199 b5 a5 2 41-c1g32 4214e2g22 43-f2g12 4415e6h42 45---- 46---- 47---- 48---- 49---- 410---- 411---- 412---- 413-f3h32 41416d1h22 41517g4h12 41618e1j42 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld 12 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r 5 1 198 d6 c6 2 5 2 197 a5 b6 2 5 3 196 e8 a6 2 5 4 195 b6 d7 2 5 5 194 c7 c7 2 56---- 57---- 58---- 59---- 510---- 511---- 512---- 5 13 193 - b7 2 5 14 - a6 a7 2 5 15 192 d7 d8 2 516-b7c82 6119g3j32 6 2 20 g2 j2 2 6321-j12 64-f5k42 65---- 66---- 67---- 68---- 69---- 610---- 611---- 612---- 613--k32 614-f1k22 615--k12 616-g5l12 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 71191-b82 72-e9a82 73189a7d92 74188d8c92 75187b8b92 76---- 77---- 78---- 79---- 710---- 711---- 712---- 713186c8a92 714185a8d102 7 15 184 e11 c10 2 7 16 183 e10 b10 2 81-h2l42 8222-l32 8 3 23 h4 l2 2 84--m12 85---- 86---- 87---- 88---- 89---- 810---- 811---- 812---- 813-g1m22 81425h3m32 815-h1m42 8 16 - h5 n1 2 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 13 product specification r 9 1 - - aa2 1 9 2 50 n3 ab1 1 9 3 49 - aa1 1 9448-w41 95---- 96---- 97---- 98---- 99---- 910---- 911---- 912---- 913-r1y31 91447n4y21 915-n2w31 9(gck1) 16 46 m3 y1 1 10(cdrst) 1 51 p2 ab2 1 10 2 54 p4 y4 1 10(gck2) 3 55 p5 ab3 1 10 4 56 r2 aa4 1 10 5 - - - - 10 6 - - - - 10 7 - - - - 10 8 - - - - 10 9 - - - - 10 10 - - - - 10 11 - - - - 10 12 - - - - 10 13 57 t1 y5 1 10(dge) 14 58 t2 aa5 1 10 15 - - ab4 1 10 16 - n5 w6 1 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 11 1 45 p1 w2 1 11 2 - m4 w1 1 11(gck0) 3 44 m2 v3 1 11 4 43 l3 u4 1 11 5 - - - - 11 6 - - - - 11 7 - - - - 11 8 - - - - 11 9 - - - - 11 10 - - - - 11 11 - - - - 11 12 - - - - 11 13 41 n1 v2 1 11 14 40 l4 v1 1 11 15 39 m1 u3 1 11 16 38 l5 u2 1 12 1 60 r4 ab5 1 12 2 61 m5 y6 1 12 3 62 r5 aa6 1 12 4 63 r6 ab6 1 12 5 64 - w7 1 12 6 - - - - 12 7 - - - - 12 8 - - - - 12 9 - - - - 12 10 - - - - 12 11 - - - - 12 12 - - - - 12 13 65 n6 y7 1 12 14 66 - aa7 1 12 15 67 r3 ab7 1 12 16 - - w8 1 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld 14 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r 13 1 37 - u1 1 13 2 - k4 t4 1 13 3 36l2t3 1 13 4 35 - t2 1 13 5 - - - - 13 6 - - - - 13 7 - - - - 13 8 - - - - 13 9 - - - - 13 10 - - - - 13 11 - - - - 13 12 - - - - 13 13 - k3 t1 1 13 14 34 l1 r4 1 13 15 32 k5 r3 1 13 16 - k2 r2 1 14 1 - m6 y8 1 14 2 - - aa8 1 14 3 69 t3 ab8 1 14 4 70 p6 w9 1 14 5 71 t4 y9 1 14 6 - - - - 14 7 - - - - 14 8 - - - - 14 9 - - - - 14 10 - - - - 14 11 - - - - 14 12 - - - - 14 13 72 p7 aa9 1 14 14 - - ab9 1 14 15 73 t5 w10 1 14 16 - - y10 1 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 15 1 31 j4 r1 1 15 2 - k1 p4 1 15 3 30 j3 p3 1 15 4 29 j2 p2 1 15 5 - - - - 15 6 - - - - 15 7 - - - - 15 8 - - - - 15 9 - - - - 15 10 - - - - 15 11 - - - - 15 12 - - - - 15 13 28 j5 p1 1 15 14 27 j1 n4 1 15 15 - - n3 1 15 16 - - n2 1 16 1 74 n7 aa10 1 16 2 - - ab10 1 16 3 75 r7 ab11 1 16 4 76 m7 w11 1 16 5 77 t6 aa11 1 16 6 - - - - 16 7 - - - - 16 8 - - - - 16 9 - - - - 16 10 - - - - 16 11 - - - - 16 12 - - - - 16 13 - - y11 1 16 14 78 - ab12 1 16 15 - - aa12 1 16 16 - - y12 1 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 15 product specification r 17 1 161 a16 a21 4 17 2 162 b13 b20 4 17 3 163 - c19 4 17 4 164 - b19 4 17 5 165 b14 c18 4 17 6 - - - - 17 7 - - - - 17 8 - - - - 17 9 - - - - 17 10 - - - - 17 11 - - - - 17 12 - - - - 17 13 166 c13 b18 4 17 14 167 a15 a19 4 17 15 168 c12 d17 4 17 16 169 b12 a18 4 18 1 160 b15 a22 4 18 2 - c14 b21 4 18 3 - g11 b22 4 18 4 159 b16 c20 4 18 5 - - - - 18 6 - - - - 18 7 - - - - 18 8 - - - - 18 9 - - - - 18 10 - - - - 18 11 - - - - 18 12 - - - - 18 13 - - c21 4 18 14 - d14 d19 4 18 15 158 - d20 4 18 16 - c15 c22 4 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 19 1 170 d13 c17 4 19 2 171 a14 b17 4 19 3 173 e13 a17 4 19 4 - a13 d16 4 19 5 - c11 c16 4 19 6 - - - - 19 7 - - - - 19 8 - - - - 19 9 - - - - 19 10 - - - - 19 11 - - - - 19 12 - - - - 19 13 - a12 b16 4 19 14 - b11 a16 4 19 15 - d11 d15 4 19 16 - a11 c15 4 20 1 - g12 d21 4 20 2 - d15 d22 4 20 3 155 e14 e20 4 20 4 154 c16 f19 4 20 5 - - - - 20 6 - - - - 20 7 - - - - 20 8 - - - - 20 9 - - - - 20 10 - - - - 20 11 - - - - 20 12 - - - - 20 13 153 f14 e21 4 20 14 152 d16 e22 4 20 15 151 f13 f20 4 20 16 150 e15 f21 4 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld 16 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r 21 1 - d10 b15 4 21 2 174 b10 a15 4 21 3 175 e12 d14 4 21 4 - f12 b14 4 21 5 178 - a14 4 21 6 - - - - 21 7 - - - - 21 8 - - - - 21 9 - - - - 21 10 - - - - 21 11 - - - - 21 12 - - - - 21 13 - - d13 4 21 14 - - c13 4 21 15 - - b13 4 21 16 - - a13 4 22 1 149 g13 f22 4 22 2 148 f15 g19 4 22 3 147 g14 g20 4 22 4 146 e16 g21 4 22 5 - - - - 22 6 - - - - 22 7 - - - - 22 8 - - - - 22 9 - - - - 22 10 - - - - 22 11 - - - - 22 12 - - - - 22 13 145 h12 g22 4 22 14 144 f16 h19 4 22 15 143 h16 h20 4 22 16 142 - h21 4 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 23 1 179 b9 a12 4 23 2 180 - d12 4 23 3 - c9 b12 4 23 4 182 - c12 4 23 5 - c10 a11 4 23 6 - - - - 23 7 - - - - 23 8 - - - - 23 9 - - - - 23 10 - - - - 23 11 - - - - 23 12 - - - - 23 13 - - b11 4 23 14 - a9 c11 4 23 15 - - d11 4 23 16 - d9 a10 4 24 1 140 g15 h22 4 24 2 139 h13 j19 4 24 3 138 g16 j20 4 24 4 137 h14 j21 4 24 5 - - - - 24 6 - - - - 24 7 - - - - 24 8 - - - - 24 9 - - - - 24 10 - - - - 24 11 - - - - 24 12 - - - - 24 13 136 h15 j22 4 24 14 135 j12 k19 4 24 15 134 k12 k20 4 24 16 - j16 k21 4 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 17 product specification r 25 1 110 r16 w22 3 25 2 111 n15 v20 3 25 3 112 m15 v21 3 25 4 113 m13 u19 3 25 5 - - - - 25 6 - - - - 25 7 - - - - 25 8 - - - - 25 9 - - - - 25 10 - - - - 25 11 - - - - 25 12 - - - - 25 13 114 p16 v22 3 25 14 115 n16 u20 3 25 15 116 l14 u21 3 25 16 117 m14 u22 3 26 1 109 n14 y22 3 26 2 108 t16 w21 3 26 3 107 r15 w20 3 26 4 106 p15 y21 3 26 5 - p14 y20 3 26 6 - - - - 26 7 - - - - 26 8 - - - - 26 9 - - - - 26 10 - - - - 26 11 - - - - 26 12 - - - - 26 13 103 p13 aa22 3 26 14 102 r13 ab22 3 26 15 101 n13 aa21 3 26 16 100 r14 ab21 3 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 27 1 118 l15 t19 3 27 2 - l13 t20 3 27 3 119 m12 t21 3 27 4 120 m16 t22 3 27 5 - - - - 27 6 - - - - 27 7 - - - - 27 8 - - - - 27 9 - - - - 27 10 - - - - 27 11 - - - - 27 12 - - - - 27 13 - k14 r19 3 27 14 - - r20 3 27 15 121 - r21 3 27 16 - - r22 3 28 1 99 t15 w19 3 28 2 97 r12 aa20 3 28 3 95 t14 y18 3 28 4 - n11 aa19 3 28 5 - p11 w17 3 28 6 - - - - 28 7 - - - - 28 8 - - - - 28 9 - - - - 28 10 - - - - 28 11 - - - - 28 12 - - - - 28 13 - m11 y17 3 28 14 - t13 aa18 3 28 15 - n10 ab18 3 28 16 - - aa17 3 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld 18 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r 29 1 - l16 p19 3 29 2 - - p20 3 29 3 122 - p21 3 29 4 123 - p22 3 29 5 - - - - 29 6 - - - - 29 7 - - - - 29 8 - - - - 29 9 - - - - 29 10 - - - - 29 11 - - - - 29 12 - - - - 29 13 - - n19 3 29 14 125 k15 n21 3 29 15 - l12 n22 3 29 16 - - m22 3 30 1 - - ab17 3 30 2 91 t12 w16 3 30 3 90 p10 y16 3 30 4 89 t11 aa16 3 30 5 - r10 ab16 3 30 6 - - - - 30 7 - - - - 30 8 - - - - 30 9 - - - - 30 10 - - - - 30 11 - - - - 30 12 - - - - 30 13 88 m10 w15 3 30 14 87 t10 y15 3 30 15 - m9 aa15 3 30 16 86 r9 ab15 3 pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank 31 1 126 k16 m19 3 31 2 - - m20 3 31 3 127 - m21 3 31 4 128 j14 l22 3 31 5 - - - - 31 6 - - - - 31 7 - - - - 31 8 - - - - 31 9 - - - - 31 10 - - - - 31 11 - - - - 31 12 - - - - 31 13 - - l21 3 31 14 - j15 l20 3 31 15 - - l19 3 31 16 131 j13 k22 3 32 1 85 p9 w14 3 32 2 84 n9 y14 3 32 3 - t9 aa14 3 32 4 83 m8 ab14 3 32 5 - t8 w13 3 32 6 - - - - 32 7 - - - - 32 8 - - - - 32 9 - - - - 32 10 - - - - 32 11 - - - - 32 12 - - - - 32 13 82 p8 y13 3 32 14 80 r8 aa13 3 32 15 - t7 ab13 3 32 16 - n8 w12 3 notes: 1. gts = global output enable, gsr = global reset/set, gck = global clock, cdrst = clock divide reset, dge = datagate enable. 2. gck, gsr, and gts pins can also be used for general purpose i/o. pin descriptions (continued) function block macro- cell pq208 ft256 fg324 i/o bank
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 19 product specification r xc2c512 jtag, power/ground, no connect pins and total user i/o device part marking figure 5: sample package with part marking pin type pq208 ft256 fg324 tck 98 p12 y19 tdi 94 r11 ab19 tdo 176 a10 c14 tms 96 n12 ab20 v ccaux (jtag supply voltage) 11 f4 f1 power internal (v cc ) 1, 53, 124 p3, k13, d12, d5 e3, aa3, n20, a20, d4 power bank 1 i/o (v ccio1 ) 33,59,79 j6, k6, l7, l8 m9, n9, p10, p11 power bank 2 i/o (v ccio2 ) 26, 204 f7, f8, g6, h6 j10,j11, k9, l9 power bank 3 i/o (v ccio3 ) 92, 105, 132 j11, k11, l9, l10 m14, n14, p12, p13 power bank 4 i/o (v ccio4 ) 133, 157, 172, 181 f9, f10, h11 j12, j13, k14, l14 ground 13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 f6, f11, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, l6, l11 d5, d18, e4, e19, j9, j14, k10, k11, k12, k13, l10, l11, l12, l13, m10, m11, m12, m13, n10, n11, n12, n13, p9, p14, v4, v19, w5, w18 no connects - - - total user i/o (includes dual function pins) 173 212 270 xc2cxxx tq144 7c device type package speed operating range this line not related to device part number r
xc2c512 coolrunner-ii cpld 20 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r ordering information part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o commercial (c) industrial (i) (1) xc2c512-7pq208c 0.5mm 35.1 7.2 plastic quad flat pack 28mm x 28mm 173 c xc2c512-10pq208c 0.5mm 35.1 7.2 plastic quad flat pack 28mm x 28mm 173 c xc2c512-7ft256c 1.0mm 32.2 4.9 fine pitch thin bga 17mm x 17mm 212 c xc2c512-7ft256i 1.0mm 32.2 4.9 fine pitch thin bga 17mm x 17mm 212 i xc2c512-10ft256c 1.0mm 32.2 4.9 fine pitch thin bga 17mm x 17mm 212 c xc2c512-7fg324c 1.0mm 39.1 5.0 fine pitch bga 23mm x 23mm 270 c xc2c512-10fg324c 1.0mm 39.1 5.0 fine pitch bga 23mm x 23mm 270 c xc2c512-7pqg208c 0.5mm 35.1 7.2 plastic quad flat pack; pb-free 28mm x 28mm 173 c xc2c512-10pqg208c 0.5mm 35.1 7.2 plastic quad flat pack; pb-free 28mm x 28mm 173 c xc2c512-7ftg256c 1.0mm 32.2 4.9 fine pitch thin bga; pb-free 17mm x 17mm 212 c xc2c512-7ftg256i 1.0mm 32.2 4.9 fine pitch thin bga; pb-free 17mm x 17mm 212 i xc2c512-10ftg256c 1.0mm 32.2 4.9 fine pitch thin bga; pb-free 17mm x 17mm 212 c xc2c512-7fgg324c 1.0mm 39.1 5.0 fine pitch bga; pb-free 23mm x 23mm 270 c xc2c512-10fgg324c 1.0mm 39.1 5.0 fine pitch bga; pb-free 23mm x 23mm 270 c xc2c512-10pq208i 0.5mm 35.1 7.2 plastic quad flat pack 28mm x 28mm 173 i xc2c512-10ft256i 1.0mm 32.2 4.9 fine pitch thin bga 17mm x 17mm 212 i XC2C512-10FG324I 1.0mm 39.1 5.0 fine pitch bga 23mm x 23mm 270 i xc2c512-10pqg208i 0.5mm 35.1 7.2 plastic quad flat pack; pb-free 28mm x 28mm 173 i xc2c512-10ftg256i 1.0mm 32.2 4.9 fine pitch thin bga; pb-free 17mm x 17mm 212 i xc2c512-10fgg324i 1.0mm 39.1 5.0 fine pitch bga; pb-free 23mm x 23mm 270 i notes: 1. c = commercial (t a = 0c to +70 c); i = industrial (t a = ?40c to +85c).. standard example: xc2c128 device speed grade package type number of pins temperature range -7 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -7 temperature range
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 21 product specification r figure 6: pq208 plastic quad flat pack vcc i/o i/o(1) i/o i/o(1) i/o i/o(1) i/o i/o(1) i/o vaux i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o v ccio2 i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o(2) i/o i/o(2) i/o i/o i/o i/o i/o(4) gnd pq208 top view vcc i/o i/o(2) i/o i/o i/o(5) vccio1 i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio3 gnd tdi i/o tms i/o tck i/o i/o i/o i/o i/o gnd (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio 4 vccio 3 i/o gnd gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio 3 i/o gnd i/o(3) i/o vccio 2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o vccio 4 i/o i/o i/o gnd tdo i/o i/o i/o vccio 4 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
xc2c512 coolrunner-ii cpld 22 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r figure 7: ft256 fine pitch thin bga ft256 bottom view 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 i/o tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(3) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) i/o i/o vcc i/o i/o i/o i/o i/o vcc i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) i/o(1) i/o i/o i/o i/o vccio4 vaux i/o i/o i/o gnd vccio4 vccio2 vccio2 gnd i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o gnd gnd gnd vccio2 i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vccio4 gnd gnd gnd vccio2 i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vccio3 gnd gnd gnd vccio1 i/o i/o i/o i/o i/o i/o gnd i/o vcc i/o i/o vccio3 gnd gnd gnd vccio1 i/o i/o i/o i/o i/o i/o vccio3 i/o i/o i/o i/o gnd vccio3 vccio1 vccio1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(2) i/o(2) i/o i/o i/o i/o i/o i/o i/o tms i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tck i/o i/o i/o i/o i/o i/o(2) vcc i/o(4) i/o i/o i/o i/o i/o i/o i/o i/o tdi i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) i/o i/o (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable a b c d e f g h j k l m n p r t
xc2c512 coolrunner-ii cpld ds096 (v3.2) march 8, 2007 www.xilinx.com 23 product specification r figure 8: fg324 fine pitch bga fg324 bottom view a b c d e f g h j k l m n p r t u v w y a a a b 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio2 i/o i/o gnd vccio4 vccio4 vccio2 gnd i/o i/o gnd i/o i/o vccio4 gnd gnd gnd vccio2 i/o i/o gnd i/o i/o vccio4 gnd gnd gnd vccio2 i/o i/o gnd i/o i/o vccio3 gnd gnd gnd vccio1 i/o i/o gnd i/o vcc vccio3 gnd gnd gnd vccio1 i/o i/o vccio1 i/o i/o gnd vccio3 vccio3 vccio1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable gnd vcc i/o i/o(1) i/o i/o i/o vaux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o(2) i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o tck i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(2) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) vcc i/o i/o i/o i/o i/o tdi tms i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(2) i/o(4) i/o vcc i/o gnd i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o(1) i/o i/o i/o i/o i/o i/o(1) i/o i/o i/o i/o i/o(3) i/o
xc2c512 coolrunner-ii cpld 24 www.xilinx.com ds096 (v3.2) march 8, 2007 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the produc ts. products are not designed to be fail-safe and are not warranted for use in applications th at pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. additional information additional information is available for the following coolrunner-ii topics: ? xapp784: bulletproof cpld design practices ? xapp375: timing model ? xapp376: logic engine ? xapp378: advanced features ? xapp382: i/o characteristics ? xapp389: powering coolrunner-ii ? xapp399: assigning vref pins to access these and all application notes with their associ- ated reference designs, click the following link and scroll down the page until you find the document you want: coolrunner-ii data sheets and application notes device packages revision history the following table shows the revision history for this document. date version revision 7/19/02 1.0 initial xilinx release. 3/15/03 2.0 added characterization data. 11/25/03 2.1 fixed two typos. 1/26/04 2.2 updated tsol; added links to data sheets and application notes. 8/03/04 2.3 pb-free documentation 10/01/04 2.4 add asynchronous preset/reset pulse width specification to ac electrical characteristics. 01/30/05 2.5 change to i ccsb max for commercial and industrial. 03/07/05 2.6 removed -6 speed grade. modified table 1, iostandards. 03/20/06 3.0 change to product specification. add warranty disclaimer. add note to pin descriptions that gck, gsr, and gts pins can also be used for general purpose i/o. 02/15/07 3.1 corrections to timing parameters t din , t sud , t psud , t phd , t ph , t slew18 , t in (hstl), t out (sstl3), and t tin (sstl3) for -6 speed grade. corrections to t din , t sud , t co , t psud , t phd , and t ph for the -7 speed grade. values now match the software. there were no changes to silicon or characterization. added xc2c512-7ft256i and xc2c512-7ftg236i packages. change to v ih specification for 2.5v and 1.8v lvcmos. 03/08/07 3.2 fixed typo in note for v il for lvcmos18; removed note for v il for lvcmos33.

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